1. Technical Field
The disclosure relates to a chip stacking structure having through-silicon vias (TSVs). Particularly, the disclosure relates to a fault-tolerant unit and a fault-tolerant method for TSV.
2. Related Art
A three-dimensional (3D) integrated circuit (IC) is a chip stacking structure formed by stacking a plurality of chips. FIG. 1 is a schematic diagram of a conventional chip stacking structure. The chip stacking structure 100 includes a chip 110 and a chip 120, and a plurality of through-silicon via (TSV) structures is disposed between the chip 110 and the chip 120. Based on considerations of circuit layout and winding, a same signal or power can be transmitted between the two adjacent chips 110 and 120 through the TSV structures. The TSV structure includes a TSV, a pad and a micro bump, wherein the TSV is disposed in the chip 110 of the upper layer, and the pad and the micro bump are disposed between the chip 110 and the chip 120.
For example, the TSV structures TSV1, TSV2 and TSV3 shown in FIG. 1 transmit a clock signal CLK of the chip 110 to different clock trees in the chip 120. The appearances of the TSV structures TSV1, TSV2 and TSV3 shown FIG. 1 are only drawn as an example. However, once the TSV structure is faulty, the 3D IC cannot normally work due to failure of signal transmission. Therefore, performance of the TSV structures is one of important factors influencing a yield of the 3D ICs.